In the related art, a technique of improving data reliability of a cache memory by using an error correction code (ECC) is introduced. In general, in order to perform operations at a high speed, a redundancy code for error correction is shorter than data in terms of a code length. In addition, in writing in a memory circuit, in general, if the code length is long, delay is increased. Therefore, it is considered to adopt an operation sequence for performing calculation of the redundancy code and its writing in a parallel manner during the writing of data bits.
By adopting the operation sequence, the delay in the calculation of the redundancy code and its writing is concealed by the delay of the writing of the long data bits, so that a high-speed write operation can be realized.
Since the delay of the writing of a nonvolatile memory cell itself is considerably larger than the delay of other circuit blocks in the nonvolatile memory circuit, the time of writing in the nonvolatile memory circuit depends on the delay of the writing of the nonvolatile memory cell itself. Therefore, although the code length of the redundancy code is set to be shorter than the length of the data bits, the delay of the writing of the redundancy code is not significantly decreased. Accordingly, in the case where a nonvolatile memory cell is used as a cache memory, since it takes a long time to calculate the redundancy code and to write it, there is a problem in that a time of data access is increased.